ast2600: Add platform peripherals (GPIO, I2C, HACE, eSPI, ADC, LPC, and stubs)#191
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garybeihl wants to merge 3 commits intorenode:masterfrom
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ast2600: Add platform peripherals (GPIO, I2C, HACE, eSPI, ADC, LPC, and stubs)#191garybeihl wants to merge 3 commits intorenode:masterfrom
garybeihl wants to merge 3 commits intorenode:masterfrom
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Aspeed_SBC: Secure Boot Controller stub returning status=idle, not-secured. Sufficient for Linux boot. Aspeed_GPIO: GPIO controller with W1C INT_STATUS, parameterized numberOfSets for 3.3V (7 sets, 208 pins) and 1.8V (2 sets, 36 pins). Per-set data, direction, and interrupt registers. Aspeed_I2C: I2C controller with 16 buses, AST2600 new-mode register layout at 0x80 stride, NACK response on empty buses, W1C interrupt status, per-bus IRQs via INumberedGPIOOutput. Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
Minimal peripheral models matching QEMU reference behavior, sufficient for Linux driver probe without errors: - PWM: Simple R/W register storage (67 registers, 0x1000 bytes) - PECI: CMD FIRE auto-complete, W1C INT_STS, success code 0x40 - XDMA: IRQ_STATUS reset 0xF8000000, W1C, IRQ_CTRL mask - RTC: Enable/unlock control, fixed time counters, W1C alarm status All peripherals implement IGPIOSender for IRQ wiring. Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
Aspeed_HACE: Hash/crypto engine with SHA-256/384/512/MD5/SHA1. Direct DMA and scatter-gather hash modes, accumulation mode for multi-request hashing, actual cryptographic computation via .NET IncrementalHash. W1C interrupt status. Aspeed_eSPI: eSPI slave controller with capability registers, CTRL with self-clearing SW reset, W1C INT_STS, INT_EN/INT_EN_CLR, VW SYSEVT with host/slave masking, per-channel TX/RX CTRL and FIFO, DMA address registers, MMBI instances. Aspeed_ADC: Dual-engine 16-channel 10-bit ADC. Data registers pack two channels per word, auto-increment sampling, threshold bounds checking with per-channel interrupt flags, W1C interrupt source register. Aspeed_LPC: 4-channel KCS interface. Per-channel IDR/ODR/STR, IBF/OBF flag management, Channel 3 dual-gate, per-channel IBF interrupt enable, IRQ aggregation, configurable chip ID. Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
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Summary
Add AST2600 platform peripheral models for Linux driver compatibility. These peripherals are not required for boot but are probed by the kernel and OpenBMC systemd services.
Tier 2 — functional peripherals
Tier 3 — stubs for driver probe
Functional peripherals
Context
With these peripherals present, Linux kernel driver probes complete without errors or timeouts, and OpenBMC systemd services (phosphor-hwmon, phosphor-pid-control, etc.) start successfully.
All models developed and validated against QEMU reference implementation and the AST2600 datasheet.
Test plan